ACCESS & DOCUMENTATION | Acoustic Parametron Ising Machine (APIM)

Overview

**SYSTEM CLASSIFICATION** Open-Source Analog Optimization Hardware — full build specification, published alongside the benchmark finding that led us not to build it. **PRIMARY MISSION** To determine, before spending money on hardware, whether a room-temperature analog oscillator network can outperform existing digital optimization software on the same class of problems — and to publish the answer either way. **INDUSTRY CHALLENGE** A large class of real-world problems — scheduling, routing, resource allocation, circuit placement — belong to a family where the number of possible solutions grows so fast that no digital computer can check them exhaustively. Two exotic hardware approaches have been built to attack this directly: quantum annealers, which require cooling to near absolute zero, and laser-based coherent Ising machines, which require specialized optical hardware. Both work, and both carry significant infrastructure cost. **WHAT WE BUILT AND TESTED** • **Room-Temperature Parametron Array:** A network of ordinary electronic oscillators — LC tank circuits and quartz crystals — each pumped at twice its natural frequency so it locks into one of two stable phase states, the physical analog of a binary variable. • **Wireless Coupling via Measurement Feedback:** Rather than physically wiring every pair of oscillators — infeasible past a few dozen elements — an FPGA continuously measures every cell's state and injects the computed interaction back in as a drive signal, the same approach used by published large-scale coherent Ising machines. • **Rigorous Head-to-Head Benchmarking:** Before any hardware was built, the full design was simulated and benchmarked against Toshiba's discrete Simulated Bifurcation algorithm — pure software — at matched computational cost and equal tuning effort on both sides, rather than the literature-default comparisons common in this field. **TARGET APPLICATIONS — AS EVALUATED** • **General Combinatorial Optimization:** Tested directly. No consistent advantage found against existing software at any problem size measured. • **Large Fixed-Topology Problems (untested, speculative):** Simulation suggests that if the coupling structure of a problem is fixed and physically wired rather than computed, very large instances (thousands of variables) could in principle be handled faster than any digital chip, because digital work grows with problem size and physical settling time does not. This case was not built, is not commercially pursued, and is published only as an open research direction. **PARTNERSHIP & TECHNICAL BRIEF** • **Development Status:** Simulation-complete; physical prototype not built. • **Collaboration Request:** None. This entry exists to document a negative result, not to solicit investment. • **Notice:** Every schematic, component value, benchmark instance, and line of simulation code behind this entry is public. There is no NDA-gated version of this project. • **Open Repository:** Full simulation code and benchmark suite available on GitHub at [github.com/shmuelbiller1/apim-benchmark-study](https://github.com/shmuelbiller1/apim-benchmark-study).

Technical Specifications

• DESIGNATION: TERRANEX APIM
• DEVELOPMENT STATUS: Simulation Complete / Hardware Not Built
• INTELLECTUAL PROPERTY: Fully open — no patents filed, no NDA
• TECHNICAL REVIEW: Full benchmark paper, simulation code, and build
• PRIMARY FUNCTION: Combinatorial optimization via a room-temperature
• SYSTEM ARCHITECTURE: Array of parametron cells (LC and quartz
• TECHNOLOGY CATEGORY: Physics-Inspired Computing / Analog Ising Machine
• INTEGRATION STRATEGY: Off-the-shelf electronic components, standard PCB
• MANUFACTURING PATH: Bench-buildable with commodity parts
• SCALABILITY PROFILE: Time-to-solution measured at TTS ~ N^2.115 —
• TARGET APPLICATIONS: Evaluated for general combinatorial optimization;
• COMMERCIAL PATHWAY: None
• PARTNERSHIP STATUS: Closed — not seeking co-development
• TECHNOLOGY READINESS: Simulation-validated; physical build assessed

Technical Documentation

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