Acoustic Parametron Ising Machine (APIM)

Codename: | Status: OPEN SOURCE / NOT PURSUING FABRICATION | Classification: UNCLASSIFIED

Overview

**SYSTEM CLASSIFICATION** Open-Source Analog Optimization Hardware — full build specification, published alongside the benchmark finding that led us not to build it. **PRIMARY MISSION** To determine, before spending money on hardware, whether a room-temperature analog oscillator network can outperform existing digital optimization software on the same class of problems — and to publish the answer either way. **INDUSTRY CHALLENGE** A large class of real-world problems — scheduling, routing, resource allocation, circuit placement — belong to a family where the number of possible solutions grows so fast that no digital computer can check them exhaustively. Two exotic hardware approaches have been built to attack this directly: quantum annealers, which require cooling to near absolute zero, and laser-based coherent Ising machines, which require specialized optical hardware. Both work, and both carry significant infrastructure cost. **WHAT WE BUILT AND TESTED** • **Room-Temperature Parametron Array:** A network of ordinary electronic oscillators — LC tank circuits and quartz crystals — each pumped at twice its natural frequency so it locks into one of two stable phase states, the physical analog of a binary variable. • **Wireless Coupling via Measurement Feedback:** Rather than physically wiring every pair of oscillators — infeasible past a few dozen elements — an FPGA continuously measures every cell's state and injects the computed interaction back in as a drive signal, the same approach used by published large-scale coherent Ising machines. • **Rigorous Head-to-Head Benchmarking:** Before any hardware was built, the full design was simulated and benchmarked against Toshiba's discrete Simulated Bifurcation algorithm — pure software — at matched computational cost and equal tuning effort on both sides, rather than the literature-default comparisons common in this field. **TARGET APPLICATIONS — AS EVALUATED** • **General Combinatorial Optimization:** Tested directly. No consistent advantage found against existing software at any problem size measured. • **Large Fixed-Topology Problems (untested, speculative):** Simulation suggests that if the coupling structure of a problem is fixed and physically wired rather than computed, very large instances (thousands of variables) could in principle be handled faster than any digital chip, because digital work grows with problem size and physical settling time does not. This case was not built, is not commercially pursued, and is published only as an open research direction. **PARTNERSHIP & TECHNICAL BRIEF** • **Development Status:** Simulation-complete; physical prototype not built. • **Collaboration Request:** None. This entry exists to document a negative result, not to solicit investment. • **Notice:** Every schematic, component value, benchmark instance, and line of simulation code behind this entry is public. There is no NDA-gated version of this project.

Technical Specifications

  • DESIGNATION: TERRANEX APIM
  • DEVELOPMENT STATUS: Simulation Complete / Hardware Not Built
  • INTELLECTUAL PROPERTY: Fully open — no patents filed, no NDA
  • TECHNICAL REVIEW: Full benchmark paper, simulation code, and build
  • PRIMARY FUNCTION: Combinatorial optimization via a room-temperature
  • SYSTEM ARCHITECTURE: Array of parametron cells (LC and quartz
  • TECHNOLOGY CATEGORY: Physics-Inspired Computing / Analog Ising Machine
  • INTEGRATION STRATEGY: Off-the-shelf electronic components, standard PCB
  • MANUFACTURING PATH: Bench-buildable with commodity parts
  • SCALABILITY PROFILE: Time-to-solution measured at TTS ~ N^2.115 —
  • TARGET APPLICATIONS: Evaluated for general combinatorial optimization;
  • COMMERCIAL PATHWAY: None
  • PARTNERSHIP STATUS: Closed — not seeking co-development
  • TECHNOLOGY READINESS: Simulation-validated; physical build assessed

Deep Technical Overview

For more than fifty years, computing performance has relied almost

entirely on shrinking transistors and increasing digital processing

density. As that scaling slows, the cost of solving large combinatorial

optimization problems continues to grow, and two exotic alternatives have

emerged: cryogenic quantum annealers and laser-based optical Ising

machines. Both require infrastructure far beyond a standard computer.

APIM investigated a third path: build the same class of solver out of

ordinary electronic parts, at room temperature, with no refrigeration and

no lasers. The idea itself is not new — it revives a 1954 concept called

the parametron, applying it with modern digital measurement feedback in

the same spirit as recently published large-scale optical Ising machines,

just implemented electronically instead of optically.

Rather than assume the physics would provide an advantage simply because

it is unconventional, we treated that as a question to test rather than a

conclusion to announce. We built a complete software model of the

intended hardware — accurate to the level of individual component

tolerances, oscillator quality factors, and feedback timing — and

benchmarked it against a real, published, production-grade digital

algorithm on identical problems, giving both sides equal effort to tune

their own settings.

The result was a negative one. At matched computational cost, the analog

design and the digital software land within roughly 15-50% of each other,

with no consistent winner across the sizes tested. Time-to-solution scales

polynomially with problem size — better than the exponential wall that

makes some problems intractable outright, but not favorably enough to

justify the added hardware complexity over software that already runs on

a laptop.

Potential application domains initially considered included:

  • Large-scale combinatorial optimization
  • Logistics and supply-chain planning
  • Financial optimization
  • Network routing
  • Scientific simulation

None of these showed a measurable advantage over the digital comparator at

the problem sizes tested. The one direction that remains open is

architectural rather than algorithmic: for very large, fixed-structure

problems where the coupling itself can be physically wired instead of

computed, the physics may outrun any digital chip simply because digital

work scales with problem size and physical settling time does not. That

case was analyzed but not built, and we are not pursuing it commercially.

The design is built entirely from commercially available components — LC

tank circuits, quartz crystals, a standard FPGA development board — with

no custom fabrication, cleanroom process, or exotic material at any stage.

Every schematic, bill of materials, and line of simulation code is

released without restriction.

We are publishing this project not as a product, but as a documented

instance of a benchmarking failure mode we believe is common in analog and

physics-inspired computing: comparing a heavily tuned proposed system

against a digital baseline that was never given the same effort. The

full methodology, code, and results are available for anyone evaluating a

similar architecture to check their own numbers against — or to find

where ours are wrong.

[ ACCESS & DOCUMENTATION ]

  • Benchmark paper, simulation code, hashed test instances, and this

complete build specification: [your GitHub repository link]

  • Permanent citable release (DOI): [your Zenodo DOI]
  • No NDA. No licensing inquiry required.

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